Espressif Systems /ESP32-S2 /TWAI0 /INT_RAW

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Interpret as INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_INT_ST)RX_INT_ST 0 (TX_INT_ST)TX_INT_ST 0 (ERR_WARN_INT_ST)ERR_WARN_INT_ST 0 (OVERRUN_INT_ST)OVERRUN_INT_ST 0 (ERR_PASSIVE_INT_ST)ERR_PASSIVE_INT_ST 0 (ARB_LOST_INT_ST)ARB_LOST_INT_ST 0 (BUS_ERR_INT_ST)BUS_ERR_INT_ST

Description

Interrupt Register

Fields

RX_INT_ST

Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.

TX_INT_ST

Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.

ERR_WARN_INT_ST

Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).

OVERRUN_INT_ST

Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.

ERR_PASSIVE_INT_ST

Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.

ARB_LOST_INT_ST

Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.

BUS_ERR_INT_ST

Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.

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